Due to the increasing density and complexity of contemporary random access memories (RAMs), it is difficult to fabricate RAMs that are completely free of defects within the memory cell array. Accordingly, to increase the yield of these devices, a portion of the memory cell array is designated as a redundant memory section. Memory cells of the redundant memory are accessed whenever it is determined that an incoming address corresponds to a defective portion of the main memory. On-chip logic circuitry is employed to store defective main memory addresses and facilitate writing and reading of data to the redundant memory. This logic circuitry includes multiple fuse groups wherein individual fuses within a fuse group are either open or closed to represent a logic state. Each fuse group thus forms a logic word corresponding to an address of a defective cell or group of cells in the main memory.
Referring to FIG. 1, a simplified block diagram of a conventional dynamic random access memory (DRAM) integrated circuit 10 is shown. DRAM 10 includes a DRAM memory block 12 having a MxN array of memory cells 15, forming M rows R.sub.1 -R.sub.M by N columns C.sub.1 -C.sub.N. Although only one memory block 12 and associated circuitry are shown in FIG. 1, there are typically several memory blocks fabricated onto a single DRAM chip. Within each MxN array, K redundant columns, C.sub.N-J to C.sub.N (where J=K-1) and Z redundant rows R.sub.M-Y to R.sub.M (where Y=Z-1) are designated for redundant memory. Row decoder logic 13 decodes a parallel row address input signal RA to enable one or more of the rows R.sub.1 to R.sub.M-Z corresponding to the row address. Likewise, one or more columns C.sub.1 to C.sub.N-K are enabled by column decoder logic 11 in response to a column address input CA. Data is either written to or read from the particular memory cell or cells 15 enabled by both row decoder 13 and column decoder 11. Data flows on bit lines BL connected to each cell, with the direction controlled by read/write signal R/W.
Column and row fuse banks 18 and 18', respectively, include multiple groups of fuses where each fuse group stores a column or row address corresponding to a defective column or row. Each fuse is a laser fusible link which is typically composed of polysilicon or metal and covered by a uniform layer of dielectric, such as silicon dioxide. After DRAM fabrication, tests are performed on the memory array to determine which rows and/or columns contain defective cells. The corresponding addresses are then written into the fuse groups by laser destruction of selective fuse links to create electrical opens. Each fuse group may contain about ten fuses to store a column or row address.
When the DRAM chip is powered up, the fuse information in the column and row fuse banks is written as parallel data into respective column and row fuse latches 16 and 16'. The fuse latches are read during the course of chip operation by associated column and row fuse decoders 14, 14'. Incoming column addresses CA to column decoder logic 11 are dynamically provided to column fuse decoder 14 which compares the address to those stored in the fuse latches 16. If there is a match, the column decoder logic 11 will not enable the column select line CSL.sub.i corresponding to the address. Instead, the column fuse decoder 14 will enable a specific one of column select lines CSL.sub.N-J to CSL.sub.N to activate a redundant column for data storage. Row fuse decoder 14' operates in conjunction with row decoder logic 13 in analogous fashion to enable any of redundant row select lines RSL.sub.M-Y to RSL.sub.M.
FIG. 2 illustrates an exemplary architecture of a prior art DRAM chip such as a 64M chip. Four 16M memory blocks 12a-12d are disposed in a region 20, with respective decoders/fuse decoders 24a-24d adjacent the respective memory blocks in a central area therebetween. Each of decoders/fuse decoders 24a-24d (hereafter, decoders 24a-24d) includes column decoder logic 11 with associated column fuse decoder 14, and/or row decoder logic 13 and associated row fuse decoder 14' discussed above. Fuse latches 26a-26d and fuse banks 28a-28d are adjacent respective decoders 24a-24d. A typical DRAM contains thousands of fuses, with each fuse connected to an associated fuse latch. As such, the fuse banks are placed close to the fuse latches and fuse decoding logic to minimize the necessary wiring. Other circuitry such as timing and control logic 31a, 31b and address buffers 41 are situated, e.g., in regions 30a and 30b away from the memory blocks.
A type of packaging technology often used for DRAM chips is known as leadframe on chip (LOC) technology, in which a leadframe is bonded to the chip surface by means of an LOC "tape". The leadframe supports connection of conductive leads or terminals to the internal electronics of the chip. The LOC tape serves as a physical connection between chip and leadframe as well as a "soft buffer" when a bondwire is connected to the tip of a lead. Bonding is only permitted on lead areas supported by the tape.
As shown in FIG. 2, LOC tape 32 runs across DRAM 10, overlaying two of the memory blocks 12a, 12b. A row of electrical contact pads 34 are disposed between top and bottom halves of the layout. Bondwires 23 electrically connect contact pads 34 to leads 33. The circuit connections to contact pads 34 include the address input lines, the R/W line, and so forth. The placement of LOC tape 32 is restricted by the fuse banks 28a-28d for reliability reasons. The LOC tape attracts moisture and therefore would be a concern for the unprotected fuse region if the tape were to run too close to the fuses. Consequently, LOC tape 32 needs to be cut to avoid running over the fuse banks. Typical tape design rules require a tape break of at least one millimeter. This reduction in overall tape length results in the lead pitch becoming smaller. A reduced lead pitch is problematic for memories in which a large number of leads need to be accommodated on a small die size, such as a 64M DRAM design based on 0.25 um technology. For instance, with chip lengths on the order of 10 mm, a 1 mm tape break tightens the lead pitch by about 10%.
As an alternative to cutting the LOC tape, the fuses could hypothetically be moved to another area of the chip, such as region 30a or 30b. Moving the fuses to one of regions 30a, 30b or elsewhere on the chip would require a large number of connecting wires to connect the fuses to the fuse latches to implement parallel fuse blow data transfer. Alternatively, the fuses could principally be moved together with the fuse latches and decode logic; however, this would also result in a prohibitively large number of connecting wires or in speed penalties. Therefore, prior art architectures place fuses close to the associated latches and decode logic and there is only a limited flexibility in moving the fuses.
Accordingly, there is a need for a memory architecture which avoids the necessity of cutting the LOC tape along with the associated reduction in lead pitch, and which does not employ an overly-complex wiring arrangement.